exception vector table

ARM64's (and in spirit RISC-V's) block of handler code at a fixed address set by the kernel; the processor jumps to a slot in it chosen by the kind of event.

On ARM64, VBAR_EL1 points to a 2 KB table of sixteen 128-byte entries selected by exception type (synchronous, IRQ, FIQ, SError) and origin; the cause is then read from ESR_EL1. RISC-V's stvec holds one handler address (or a vectored table for interrupts) and scause gives the cause.