Skip to content
Free public beta until December 4, 2026: every course is open, no card needed. After that, the first chapter of each course stays free and full access is a one-time $39 ($19 for up to 100 founding members chosen for helpful feedback). Your progress is kept. How the beta works

interrupt controller

The hardware that collects interrupt requests from devices and timers and delivers them to the right core.

An interrupt controller (x86-64 local APIC and I/O APIC, ARM GIC, RISC-V PLIC/AIA with the CLINT/ACLINT timer) prioritizes, routes and masks interrupt sources and signals the target core.

See also

bit mask external interrupt
Read the full section →