memory consistency model
The rules that say in which orders other cores may see one core's loads and stores to different addresses.
A memory consistency model defines which values loads may return in a multi-threaded execution, i.e. which reorderings of memory operations to different locations other cores may observe: sequential consistency, x86-TSO, Arm's other-multi-copy-atomic weak model, RISC-V RVWMO, and the C++ memory model on top.
See also