five-stage pipeline

The textbook pipeline: instruction fetch, decode and register read, execute, memory access, and write-back, one cycle each.

The classic five-stage RISC pipeline has stages instruction fetch (IF), instruction decode and register read (ID), execute or address calculation (EX), memory access (MEM) and register write-back (WB); it suits load/store ISAs such as RISC-V and is the model for this course's pipeline-sim widget.