load-use stall
The one-cycle wait when an instruction needs a value a load is still reading from memory; forwarding can't hide it, because the value doesn't exist yet.
In the five-stage pipeline a loaded value is available only at the end of the memory stage, so an instruction that uses it immediately must stall one cycle even with forwarding; compilers schedule an independent instruction into that slot.
Examples
ldr x1, [x0]thenadd x2, x1, #1costs one stall cycle in the five-stage pipeline, even with forwarding.
See also