latency staircase
The step-shaped graph you get by timing memory accesses over bigger and bigger data: flat while the data fits in a cache level, then a jump up each time it no longer fits.
A latency staircase plots average dependent-load latency (from a pointer-chasing loop over a randomly permuted buffer) against working-set size on a log scale; plateaus correspond to L1, L2, L3 and DRAM, and the step positions estimate each level's capacity on that machine.
See also