load-linked/store-conditional
A pair of instructions for atomic updates: the load marks the address, and the store succeeds only if nobody else wrote it in between; otherwise the code tries again.
Load-linked/store-conditional splits an atomic read-modify-write into a load that sets a reservation on an address (ARM64 ldxr/ldaxr, RISC-V lr.w/lr.d) and a store that succeeds only if the reservation is intact, writing a status register (ARM64 stxr: 0 success; RISC-V sc: 0 success); a failed store-conditional is retried.