memory barrier
An instruction that stops the core from letting memory operations on one side of it be seen as happening on the other side.
A memory barrier (fence) orders the memory operations before it with respect to those after it as observed by other cores: x86-64 mfence (and lock-prefixed instructions) for store-load order, ARM64 dmb ish / dmb ishld / dmb ishst, RISC-V fence rw,rw and its narrower forms; a barrier does not write caches back to memory.