RISC-V vector extension

RISC-V's optional SIMD extension, where the program asks how many elements the hardware will handle on each pass of a loop.

The RISC-V V extension (RVV 1.0) provides 32 vector registers of implementation-defined length VLEN; vsetvli sets the element width, register grouping (LMUL) and the active vector length vl = min(remaining elements, hardware maximum) for each strip of a loop.