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predicate register

An SVE register holding one on/off bit per lane, which decides which lanes an instruction works on; ARM64's counterpart to AVX-512's opmask registers.

SVE's predicate registers p0-p15 hold one bit per byte of vector length; instructions governed by p0-p7 act only on active lanes (merging with /m or zeroing with /z), and whilelo builds a predicate covering the elements left in a loop.

See also

Scalable Vector Extension opmask register AVX-512
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