Skip to content
Free public beta until December 4, 2026: every course is open, no card needed. After that, the first chapter of each course stays free and full access is a one-time $39 ($19 for up to 100 founding members chosen for helpful feedback). Your progress is kept. How the beta works

Scalable Vector Extension

An optional ARM64 extension whose vector length is chosen by each chip (128 to 2048 bits), so the same code runs on narrow and wide hardware.

SVE/SVE2 provides z0-z31 vector registers of an implementation-defined length (a multiple of 128 bits up to 2048), predicate registers p0-p15 and instructions such as whilelo and incw that let one loop adapt to any vector length; it is implemented in e.g. AWS Graviton3/4 and Fujitsu A64FX but not in Apple M-series cores.

See also

predicate register vector-length agnostic SIMD register instruction set extension
Read the full section →